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1 12-bit, 10-bit and 8-bit, 1msps sar adcs isl26712, isl26710, ISL26708 the isl26712, isl26710, ISL26708 are 12-bit, 10-bit and 8-bit, 1msps sampling sar-type adcs feat uring excellent linearity over supply and temperature variations. the robust, fully-differential input offers high impedance to minimize errors due to leakage currents, and the specified measur ement accuracy is maintained with input signals up to the supply rails. the reference accepts inputs from 0.1v to 2.2v for 3v operation and 0.1v to 3.5v for 5v operation, providing design flexibility in a wide variety of applications. the isl26712/10/08 also features up to 8kv human body model esd survivability. the serial digital interface is spi compatible and is easily interfaced to popular fpgas and microcontrollers. power dissipation is 8.5mw at a sampling rate of 1msps, and just 5w between conversions utilizing auto power-down mode (with a 5v supply), making the isl26712/10/08 excellent solutions for remote industrial sensors and battery-powered instruments. the isl26712/10/08 are available in an 8 ld tdfn or an sot-23 package, and are specified for operation over the industrial temperature range (?40c to +85c). features ? differential input ? simple spi-compatible serial digital interface ? guaranteed no missing codes ? 1mhz sampling rate ? 3v or 5v operation ?low operating current - 1.25ma at 1msps with 3v supplies - 1.70ma at 1msps with 5v supplies ? power-down current between conversions: 1a ? excellent differential non-linearity ? low thd: -83db (typ) ? pb-free (rohs compliant) ? available in tdfn package (3x3mm) ? available in sot-23 package applications ? remote data acquisition ? battery operated systems ? industrial process control ? energy measurement ? data acquisition systems ? pressure sensors ? flow controllers figure 1. block diagram figure 2. isl26712 differenti al linearity error vs code serial interface vdd vref gnd ain+ ain ? sclk sdata cs dac dac sar logic vref -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 0 1024 2048 3072 4096 code dnl (lsb) september 5, 2012 fn7999.3 caution: these devices are sensitive to electrostatic discharge; follow proper ic handling procedures. 1-888-intersil or 1-888-468-3774 | copyright intersil americas inc. 2012. all rights reserved intersil (and design) is a trademark owned by intersil corporation or one of its subsidiaries. all other trademarks mentioned are the property of their respective owners.
isl26712, isl26710, ISL26708 2 fn7999.3 september 5, 2012 typical connection diagram pin configurations isl26712/10/08 (8 ld tdfn) top view isl26712/10/08 (8 ld sot-23) top view vref ain+ ain? gnd vdd sclk sdata cs ref p-p + + +3v/5v supply p/c vref serial interface 10f 0.1f ref p-p vref ain+ ain- gnd 1 2 3 4 8 7 6 5 v dd sclk sdata cs v dd sclk sdata cs 1 2 3 4 8 7 6 5 vref ain+ ain- gnd pin description isl26712/10/08 description pin name pin number (tdfn) pin number (sot-23) vdd 8 1 supply voltage, +2.7v to 5.25v. sclk 7 2 serial clock inpu t. controls digital i/o timing and clocks the conversion. sdata 6 3 digital conversion output. cs 5 4 chip select input. generally controls the start of a conversion though not always the sampling signal. gnd 4 5 ground ain? 3 6 negative analog input. ain+ 2 7 positive analog input. vref 1 8 reference voltage. pin-compatible family part number resolution (bits) isl26712 12 isl26710 10 ISL26708 8
isl26712, isl26710, ISL26708 3 fn7999.3 september 5, 2012 ordering information part number (note 4) part marking vdd range (v) temp range (c) package (pb-free) pkg. dwg. # isl26712irtz (note 3) 6712 2.7 to 5.25 -40 to +85 8 ld tdfn l8.3x3i isl26712irtz-t (notes 1, 3) 6712 2.7 to 5.25 -40 to +85 8 ld tdfn l8.3x3i isl26712irtz-t7a (notes 1, 3) 6712 2.7 to 5.25 -40 to +85 8 ld tdfn l8.3x3i isl26710irtz (note 3) 6710 2.7 to 5.25 -40 to +85 8 ld tdfn l8.3x3i isl26710irtz-t (notes 1, 3) 6710 2.7 to 5.25 -40 to +85 8 ld tdfn l8.3x3i isl26710irtz-t7a (notes 1, 3) 6710 2.7 to 5.25 -40 to +85 8 ld tdfn l8.3x3i ISL26708irtz (note 3) 6708 2.7 to 5.25 -40 to +85 8 ld tdfn l8.3x3i ISL26708irtz-t (notes 1, 3) 6708 2.7 to 5.25 -40 to +85 8 ld tdfn l8.3x3i isl26712ihz-t (notes 1, 2) 6712 (note 5) 2.7 to 5.25 -40 to +85 8 ld sot-23 p8.064 isl26712ihz-t7a (notes 1, 2) 6712 (note 5) 2.7 to 5.25 -40 to +85 8 ld sot-23 p8.064 isl26710ihz-t (notes 1, 2) 6710 (note 5) 2.7 to 5.25 -40 to +85 8 ld sot-23 p8.064 isl26710ihz-t7a (notes 1, 2) 6710 (note 5) 2.7 to 5.25 -40 to +85 8 ld sot-23 p8.064 ISL26708ihz-t (notes 1, 2) 6708 (note 5) 2.7 to 5.25 -40 to +85 8 ld sot-23 p8.064 ISL26708ihz-t7a (notes 1, 2) 6708 (note 5) 2.7 to 5.25 -40 to +85 8 ld sot-23 p8.064 notes: 1. please refer to tb347 for details on reel specifications. 2. these intersil pb-free plastic packaged products employ specia l pb-free material sets; molding compounds/die attach materials and nipdau plate - e4 termination finish, which is rohs compliant and compatible with both snpb and pb-free solder ing operations. intersil pb-fre e products are msl classified at pb-free peak reflow temp eratures that meet or exceed the pb-fr ee requirements of ipc/jedec j std-020. 3. these intersil pb-free plastic packaged products employ spec ial pb-free material sets, molding compounds/die attach materials , and 100% matte tin plate plus anneal (e3 termination finish , which is rohs compliant and compatible wi th both snpb and pb-free soldering opera tions). intersil pb- free products are msl classified at pb-free peak reflow temperat ures that meet or exceed the pb-free requirements of ipc/jedec j std-020. 4. for moisture sensitivity level (msl), please see device information page fo isl26712, isl26710, ISL26708 . for more information on msl please see techbrief tb363 . 5. the part marking is located on the bottom of the part.
isl26712, isl26710, ISL26708 4 fn7999.3 september 5, 2012 table of contents absolute maximum ratings . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 thermal information . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 electrical specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 5 timing specifications . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 7 typical performance characteristics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 9 functional description . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 adc transfer function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 analog input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 13 voltage reference input . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 14 converter operation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15 short cycling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 power-on reset . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 acquisition time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 power vs throughput rate . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 serial digital interface . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 data format . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 terminology . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 signal-to-(noise + distortion) ratio (sinad). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 total harmonic distortion. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 peak harmonic or spurious noise (sfdr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 17 intermodulation distortion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 aperture delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 aperture jitter. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 full power bandwidth . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 common-mode rejection ratio (cmrr). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 integral nonlinearity (inl). . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 differential nonlinearity (dnl) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 zero-code error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 positive gain error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 negative gain error . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 track and hold acquisition time . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 power supply rejection ratio (psrr) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 application hints . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 grounding and layout . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 18 revision history. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 products . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 19 small outline transistor plastic packages (sot23-8) . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 p8.064 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 20 package outline drawing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21 l8.3x3i . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
isl26712, isl26710, ISL26708 5 fn7999.3 september 5, 2012 absolute maximum rating s thermal information any pin to gnd . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to +6.0v analog input to gnd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to v dd + 0.3v digital i/o to gnd. . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -0.3v to v dd + 0.3v digital input voltage to gnd . . . . . . . . . . . . . . . . . . . . . . -0.3v to v dd + 0.3v maximum current in to any pin . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 10ma esd rating human body model (tested per jesd22-a114f) . . . . . . . . . . . . . . . . 8kv machine model (tested per jesd22-a115b) . . . . . . . . . . . . . . . . . 400v charged device model (tested per jesd22-c101e) tdfn package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 2.0kv sot-23 package . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1.5kv latch up (tested per jesd78c; class 2, level a) . . . . . . . . . . . . . . . 100ma thermal resistance (typical) ja (c/w) jc (c/w) 8 ld tdfn package (notes 6, 8) . . . . . . . . . 41 6 8 ld sot-23 package (notes 7, 9). . . . . . . . 135 99 operating temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . -40c to +85c storage temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .-65c to +150c junction temperature . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . .+150c pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . see link below http://www.intersil.com/ pbfree/pb-freereflow.asp caution: do not operate at or near the maximum ratings listed for extended periods of time. exposure to such conditions may adv ersely impact product reliability and result in failures not covered by warranty. notes: 6. ja is measured in free air with the componen t mounted on a high effective thermal conduc tivity test board with ?direct attach? fe atures. see tech brief tb379. 7. ja is measured with the component mounted on a high effective thermal conductivity test board in free air. see tech brief tb379 for details. 8. for jc , the ?case temp? location is the center of the exposed metal pad on the package underside. 9. for jc , the ?case temp? location is taken at the package top center. electrical specifications v dd = +3.0v to +3.6v, f sclk = 18mhz, f s = 1msps, v ref = 2.0v; v dd = +4.75v to +5.25v, f sclk = 18mhz, f s =1msps, v ref = 2.5v; v cm = v ref , unless otherwise noted. typical values are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +85c. symbol parameter test conditions isl26712 isl26710 ISL26708 units min (note 10) typ max (note 10) min (note 10) typ max (note 10) min (note 10) typ max (note 10) dynamic performance sinad signal-to (noise + distortion) ratio f in = 100khz v dd = +4.75v to +5.25v 70.0 71.4 61.0 61.6 49.0 49.8 db f in = 100khz v dd = +3.0v to +3.6v 68.5 70.5 60.7 61.5 49.0 49.8 db thd total harmonic distortion f in = 100khz v dd = +4.75v to +5.25v -84 -76 -82 -74 -75 -60 db f in = 100khz v dd = +3.0v to +3.6v -84 -74 -82 -72 -73 -60 db sfdr spurious free dynamic range f in = 100khz v dd = +4.75v to +5.25v -87 -76 -82 -76 -68 -60 db f in = 100khz v dd = +3.0v to +3.6v -85 -74 -82 -74 -68 -60 db imd intermodulation distortion 2nd and 3rd order, f in = 90khz, 110khz -89 -83 -81 db tpd aperture delay 1 1 1 ns tpd aperture jitter 15 15 15 ps 3db full power bandwidth @ ?3db 15 15 15 mhz dc accuracy nresolution 12 10 8 bits inl integral nonlinearity -1 0.4 1-0.5 0.1 0.5 -0.2 0.03 0.2 lsb dnl differential nonlineari ty guaranteed no missing codes -0.95 0.3 0.95 -0.5 0.1 0.5 -0.2 0.03 0.2 lsb offset zero-code error zero volt differential input -6 0.2 6-2.5 0.2 2.5 -1.25 0.03 1.25 lsb
isl26712, isl26710, ISL26708 6 fn7999.3 september 5, 2012 gain positive gain error ref input range -2 0.1 2-1 0.1 1 -0.75 0.04 0.75 lsb negative gain error -2 0.1 2-1 0.1 1 -0.75 0.04 0.75 lsb analog input (note 11) |ain| full-scale input span 2 x v ref (ain+) ? (ain?) (ain+) ? (ain?) (ain+) ? (ain?) v ain+, ain?, absolute input voltage range ain+ v cm = v ref v cm v ref /2 v cm v ref /2 v cm v ref /2 v ain? v cm v ref /2 v cm v ref /2 v cm v ref /2 v i leak input dc leakage current -1 1 -1 1 -1 1 a c vin input capacitance track/hold mode 13/5 13/5 13/5 pf reference input vref vref input voltage range v dd = 3v (1% tolerance for specified performance) 2.0 2.0 2.0 v v dd = 5v (1% tolerance for specified performance) 2.5 2.5 2.5 v i leak dc leakage current -1 1 -1 1 -1 1 a c ref vref input capacitance track/hold mode 21/18.5 21/18.5 21/18.5 pf logic inputs v ih input high voltage 2.4 2.4 2.4 v v il input low voltage 0.8 0.8 0.8 v i leak input leakage current -1 1 -1 1 -1 1 a c in input capacitance 10 10 10 pf logic outputs v oh output high voltage i source = 200a v dd - 0.3 v dd - 0.3 v dd - 0.3 v v ol output low voltage i sink = 200a 0.4 0.4 0.4 v i oz floating-state output current -1 1 -1 1 -1 1 a c out floating-state output capacitance 10 10 10 pf output coding two?s complement conversion rate t conv conversion time f sclk = 18mhz 888 888 888 ns t acq acquisition time f sclk = 18mhz 200 200 200 ns f max throughput rate 1000 1000 1000 ksps power requirements v dd positive supply voltage range 2.73.62.73.62.73.6 v 4.75 5.25 4.75 5.25 4.75 5.25 v electrical specifications v dd = +3.0v to +3.6v, f sclk = 18mhz, f s = 1msps, v ref = 2.0v; v dd = +4.75v to +5.25v, f sclk = 18mhz, f s =1msps, v ref = 2.5v; v cm = v ref , unless otherwise noted. typical values are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +85c. (continued) symbol parameter test conditions isl26712 isl26710 ISL26708 units min (note 10) typ max (note 10) min (note 10) typ max (note 10) min (note 10) typ max (note 10)
isl26712, isl26710, ISL26708 7 fn7999.3 september 5, 2012 i dd positive supply input current static 111 a dynamic 3v 1250 1250 1250 a 5v 1700 1700 1700 a power dissipation static mode v dd = 3v 333 w v dd = 5v 555 w dynamic v dd = 3v, f smpl =1msps 3.75 3.75 3.75 mw v dd = 5v, f smpl =1msps 8.50 8.50 8.50 mw notes: 10. compliance to datasheet limits is assured by one or more methods: production test, characterization and/or design. 11. the absolute voltage applied to each analog input must be between gnd and v dd to guarantee datasheet performance. electrical specifications v dd = +3.0v to +3.6v, f sclk = 18mhz, f s = 1msps, v ref = 2.0v; v dd = +4.75v to +5.25v, f sclk = 18mhz, f s =1msps, v ref = 2.5v; v cm = v ref , unless otherwise noted. typical values are at t a = +25c. boldface limits apply over the operating temperature range, -40c to +85c. (continued) symbol parameter test conditions isl26712 isl26710 ISL26708 units min (note 10) typ max (note 10) min (note 10) typ max (note 10) min (note 10) typ max (note 10) timing specifications v dd = 3.0v to 3.6v, f sclk = 18mhz, f s = 1msps, v ref = 2.0v; v dd = 4.75v to 5.25v, f sclk =18mhz, f s =1msps, v ref =2.5v; v cm = v ref unless otherwise noted. boldface limits apply over the operatin g temperature range, -40c to +85c. symbol parameter (note 12) test conditions min (note 10) typ max (note 10) units fsclk clock frequency 0.01 18 mhz t sclk clock period 55 ns t acq acquisition time (note 13) ns t conv conversion time 888 ns t csw cs pulse width 10 ns t css cs falling edge to s clk falling edge setup time 10 ns t cdv cs falling edge to sdata valid 20 ns t clkdv sclk falling edge to sdata valid 40 ns t sdh sclk falling edge to sdata hold 10 ns t sw sclk pulse width 0.4 x t sclk 0.6 x t sclk ns t disable csb rising edge to sdata disable time (note 14) extrapolated back to true bus relinquish 10 35 ns t quiet quiet time before sample 60 ns notes: 12. limits established by characterization and are not production tested. 13. see ?acquisition time? on page 17. 14. during characterization, t disable is measured from the release poin t with a 10pf load (see figure 4).
isl26712, isl26710, ISL26708 8 fn7999.3 september 5, 2012 12 bit sdata t csw t cdv t css t conv t quiet t sw t clkdv t acq 10 bit sdata 12 3456789 10 11 12 13 14 15 16 00 0d11d10 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 00 0 d9 d8 d7 d6 d5 d4 d3 d2 d1 d0 00 0 d7d6d5d4 d3 d2 d1 d0 hi-z t acq t acq 8 bit sdata hi-z hi-z 0 0 0 t disable figure 3. serial interface timing diagram figure 4. equivalent load circuit output pin c l 10pf vdd 2.85k r l
isl26712, isl26710, ISL26708 9 fn7999.3 september 5, 2012 typical performance characteristics figure 5. isl26712 sinad vs analog input frequency for various supply voltages figure 6. isl26712 dynamic performance with vdd = 5v figure 7. cmrr vs frequency for vdd = 5v figure 8. typical dnl for the isl26712 for vdd = 5v figure 9. psrr vs supply ripple frequency without supply decoupling figure 10. typical inl for the isl26712 for vdd = 5v 55 60 65 70 75 10 100 1k input frequency (khz) sinad (dbc) 2.7v 3.6v 4.75v 5.25v -140 -120 -100 -80 -60 -40 -20 0 0 100 200 300 400 500 frequency (khz) 8192-point fft f sample = 1msps f in = 95.2khz sinad = 72.0db thd = -91db sfdr = 93db amplitude (dbfs) -100 -90 -80 -70 -60 -50 -40 -30 -20 -10 0 10k 100k 1k 10k frequency (hz) cmrr (db) -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 0 1024 2048 3072 4096 code dnl (lsb) -120 -100 -80 -60 -40 -20 0 0 100 200 300 400 500 600 700 800 900 1000 frequency (khz) 250mvp-p sine wave on vdd no decoupling on vdd psrr (db) -1.0 -0.8 -0.6 -0.4 -0.2 0.0 0.2 0.4 0.6 0.8 1.0 0 1024 2048 3072 4096 code inl (lsb)
isl26712, isl26710, ISL26708 10 fn7999.3 september 5, 2012 figure 11. change in dnl vs vref for the isl26712 for vdd = 5v figure 12. change in inl vs vref for the isl26712 for vdd = 3v figure 13. change in dnl vs vref for the isl26712 for vdd = 3v figure 14. change in offset error vs reference voltage for vdd = 5v and 3v for the isl26712 figure 15. change in inl vs vref for the isl26712 for vdd = 5v figure 16. change in enob vs reference voltage for vdd = 5v and 3v for the isl26712 typical performance characteristics (continued) -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 v ref (v) dnl (lsb) neg dnl pos dnl -2.0 -1.5 -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 0.0 0.5 1.0 1.5 2.0 2.5 inl (lsb) v ref (v) neg inl pos inl -1.0 -0.5 0.0 0.5 1.0 1.5 2.0 2.5 0.0 0.5 1.0 1.5 2.0 2.5 v ref (v) dnl (lsb) neg dnl pos dnl -2 -1 0 1 2 3 4 5 6 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 zero code error (lsb) v ref (v) 3v v dd 5v v dd -5 -4 -3 -2 -1 0 1 2 3 4 5 0.0 0.5 1.0 1.5 2.0 2.5 3.0 3.5 inl (lsb) v ref (v) neg inl pos inl 7.0 7.5 8.0 8.5 9.0 9.5 10.0 10.5 11.0 11.5 12.0 0.00.51.01.52.02.53.03.5 enob (bits) v ref (v) 5v v dd 3v v dd
isl26712, isl26710, ISL26708 11 fn7999.3 september 5, 2012 figure 17. histogram of 10, 000 conversions of a dc input for the isl26712 with vdd = 5v figure 18. typical dnl for the isl26710 for vdd = 5v figure 19. isl26710 dynamic performance with vdd = 5v figure 20. typical inl for the isl26710 for vdd = 5v figure 21. typical dnl for the ISL26708 for vdd = 5v figure 22. typical inl for the ISL26708 for vdd = 5v typical performance characteristics (continued) 0 10k 20k 30k 40k 50k 60k 70k 2044 2045 2046 2047 2048 2049 2050 code 65,516 codes 10 codes 10 codes hits -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0 256 512 768 1024 code dnl (lsb) -140 -120 -100 -80 -60 -40 -20 0 0 100 200 300 400 500 frequency (khz) amplitude (dbfs) 8192-point fft f sample = 1msps f in = 95.2khz sinad = 61.6db thd = -75db sfdr = 81db -0.5 -0.4 -0.3 -0.2 -0.1 0 0.1 0.2 0.3 0.4 0.5 0 2 5 6 5 1 2 7 6 8 1 0 2 4 code inl (lsb) -0.25 -0.20 -0.15 -0.10 -0.05 0.00 0.05 0.10 0.15 0.20 0.25 0 32 64 96 128 160 192 224 256 code dnl (lsb) -0.25 -0.20 -0.15 -0.10 -0.05 0.00 0.05 0.10 0.15 0.20 0.25 0 32 64 96 128 160 192 224 256 code inl (lsb)
isl26712, isl26710, ISL26708 12 fn7999.3 september 5, 2012 figure 23. ISL26708 dynamic performance with vdd = 5v typical performance characteristics (continued) -140 -120 -100 -80 -60 -40 -20 0 0 100 200 300 400 500 frequency (khz) 8192-point fft f in = 95.2khz sinad = 49.8db thd = -76db sfdr = 67db amplitude (dbfs) f sample = 1msps
isl26712, isl26710, ISL26708 13 fn7999.3 september 5, 2012 functional description the isl26712/10/08 are based on a successive approximation register (sar) architecture utilizing capacitive charge redistribution digital-to-analog converters (dacs). figure 24 shows a simplified representation of the converter. during the acquisition phase (acq), the differential input is stored on the sampling capacitors (cs). the comparator is in a balanced state since the switch across its inputs is closed. the signal is fully acquired after t acq has elapsed and the switches then transition to the conversion phase (conv) so the stored voltage may be converted to digital format. the comparator will become unbalanced when the differential switch opens and the input switches transition (assuming that the stored voltage is not exactly at mid-scale). the comparator output reflects whether the stored voltage is above or below mid-scale, which sets the value of the msb. the sar logic then forces the capacitive dacs to adjust up or down by one quarter of full-scale by switching in binarily weighted capacitors. again, the comparator output reflects whether the stored voltage is above or below the new value, setting the value of the next lowest bit. this process repeats until all 12 bits have been resolved. an external clock must be applied to the sclk pin to generate a conversion result. the allowable frequency range for sclk is 10khz to 18mhz (556sps to 1msp s). serial output data is transmitted on the falling edge of sclk. the receiving device (fpga, dsp or microcontroller) ma y latch the data on the rising edge of sclk to maximize set-up and hold times. a stable, low-noise reference voltage must be applied to the vref pin to set the full-scale input range and common-mode voltage. see ?voltage reference input? on page 14 for more details. adc transfer function the output coding for the isl 26712/10/08 is twos complement. the first code transition occurs at successive lsb values (i.e., 1 lsb, 2 lsb, and so on). the lsb size of the isl26712 is 2*vref/4096, while the lsb size of the isl26710 is 2*vref/1024 and the ISL26708 is 2*vref/512. the ideal transfer characteristic of the isl26712/10/08 is shown in figure 25. analog input the isl26712/10/08 feature a fu lly differential input with a nominal full-scale range equal to twice the applied vref voltage. each input swings vref v p-p , 180 out-of-phase from one another for a total differential input of 2*vref (refer to figure 26). differential signaling offers seve ral benefits over a single-ended input, such as: ? doubling of the full-scale in put range (and therefore the dynamic range) ? improved even order harmonic distortion ? better noise immunity due to common mode rejection figure 27 shows the relationship between the reference voltage and the full-scale input range for two different values of vref. note that there is a trade-off between vref and the allowable common mode input voltage (vcm). the full-scale input range is proportional to vref; therefore the vcm range must be limited for larger values of vref in order to keep the absolute maximum and minimum voltages on the ain+ and ain? pins within specification. figures 28 and 29 illustrate this relationship for 5v and 3v operation, respectively. the dashed lines show the theoretical vcm range based solely on keeping the ain+ and ain? pins within the supply rail s. additional re strictions are imposed due to the required headroom of the input circuitry, resulting in practical limits shown by the shaded area. figure 24. sar adc architectural block diagram ain+ ain? vref acq conv acq acq conv conv dac dac sar logic c s c s 1lsb = 2?vref/4096 100...000 100...001 100...010 111...111 000...000 000...001 011...110 011...111 adc code analog input ain+ ? (ain?) ? vref + ?lsb +vref ? 1?lsb 0v +vref ? 1lsb figure 25. ideal transfer characteristics figure 26. differential input signaling v cm v ref(p-p) v ref(p-p) ain+ ain?
isl26712, isl26710, ISL26708 14 fn7999.3 september 5, 2012 voltage reference input an external low-noise reference voltage must be applied to the vref pin to set the full-scale input range of the converter. the reference input accepts voltages ranging from 0.1v to 2.2v for 3v operation and 0.1v to 3.5v for 5v operation. the device is specified with a reference voltag e of 2.5v for 5v operation and 2.0v for 3v operation. figures 30 and 31 illustrate po ssible voltage reference options for the isl267440/isl26750a or isl267817. figure 30 uses the precision isl21090 voltage reference which exhibits exceptionally low drift and low noise. the isl21090 must use a power supply greater than 4.7v. the vref input pin of the isl267xx devices uses very low current, so the decoupling capacitor can be small (0.1f). figure 31 illustrates the isl21010 voltage reference being used with these adcs. the isl21010 series voltage references have higher noise and drift than the isl26090 devices, but they consume very low operating current and are excellent for battery-powered applications. figure 27. relationship between vref and full-scale range 3.0 5.0 2.0 1.0 4.0 ai n+ ai n? vcm 2.0v p- p vref = 2v 3.0 5.0 2.0 1.0 4.0 ai n+ ai n? vcm 2.5v p- p vref = 2.5v t v t v figure 28. relationship betw een vref and vcm for vdd = 5v 3.0 5.0 2.0 1.0 4.0 vref vcm 0.5 1.0 1.5 2.0 2.5 3.0 3.5 3.25v 1.75v 4.25v figure 29. relationship betw een vref and vcm for vdd = 3v 1.5 2.0 1.0 0.5 vref vcm 0.25 0.50 0.75 1.00 2.5 2.00 1.25 1.50 1.75 3.0 1.0v 2.0v
isl26712, isl26710, ISL26708 15 fn7999.3 september 5, 2012 converter operation the isl26712, isl26710 and ISL26708 are designed to minimize power consumption by only powering up the sar comparator during conversion time. when the converter is in track mode (its sample capacitors are tracking the input signal) the sar comparator is powered down. the state of the converter is dictated by the logic state of cs . when cs is high the sar comparator is powered down while the sampling capacitor array is tracking the input. when cs transitions low, the capacitor array immediately captures the analog signal that is being tracked. after cs is taken low, the sclk pin is toggled 16 times. for the first 3 clocks, the comparator is powered up and auto-zeroed, then the sar decision process is begun. this process uses 12 sclk cycles for the 12-bit isl26712. each sar decision is presented to the sdata output on the next clock cycle after the sar decision is performed. the sar process (12 bits) is completed on sclk cycle 15. at this point in time, the sar comparator is powered down and the capacitor array is placed back into track mode. the last sar comparator decision is output from sdata on the 16th sclk cycle. when the last data bit is output from sdata the outp ut switches to a logic 0 until cs is taken high, at which time, the sdata output enters a high-z state. the isl26710 and ISL26708 will take fewer clock cycles for their sar decisions and will output fewer data bits. the extra bits following the output of the lsb will be logic zeroes. figures 32, 33, and 34 illustrate the system timing for the 12-, 10- and 8-bit converters respectively. figure 30. precision voltage reference for +5v supply 1 2 3 4 8 7 6 5 dnc vin comp gnd dnc dnc vout trim 0.1f vdd 0.1f 2.5v vref 0.1f bulk + 5v isl21090 isl267440 isl267450a figure 31. voltage reference for +2.7v to +3.6v, or for +5v supply isl267817 vdd 0.1f vref 0.1f bulk + +2.7v to +3.6v isl21010 gnd vin vout 1 2 3 0.1f 1.25, 2.048 or 2.5v or +5v
isl26712, isl26710, ISL26708 16 fn7999.3 september 5, 2012 figure 32. isl26712 system timing figure 33. isl26710 system timing figure 34. ISL26708 system timing
isl26712, isl26710, ISL26708 17 fn7999.3 september 5, 2012 short cycling in cases where a lower resolution conversion is acceptable, cs can be pulled high before all sclk falling edges have elapsed. this is referred to as short cycling, and it can be used to further optimize power consumption. in this mode a lower resolution result will be output, but the adc will enter st atic mode sooner and exhibit a lower average power consumption than if the complete conversion cycle were carried out. the minimum acquisition time (t acq ) requirement of 200ns must be met for the next conversion to be valid. power-on reset when power is first applied, the isl26712/10/08 performs a power-on reset that requires approximately 2.5ms to execute. after this is complete, a single dummy conversion must be executed (by taking cs low) in order to initialize the switched capacitor track and hold. the dummy conversion cycle will take 1s with an 18mhz sclk. once the dummy cycle is complete, the adc mode will be determined by the state of cs . regular conversions can be started immediately after this dummy cy cle is completed and time has been allowed for proper acquisition. acquisition time to achieve the maximum sample rate (1 msps) in the isl26712 device, the maximum acquisitio n time is 200ns. for slower conversion rates, or for conversions performed using a slower sclk value than 18mhz, the minimum acquisition time is 200ns. this same minimum applies to the isl26710 and ISL26708. this minimum acquisition time applies to all the devices if short cycling is utilized. power vs throughput rate the isl26712/10/08 provide reduced power consumption at lower conversion rates by automatically switching into a low-power mode after completing a conversion. the average power consumption of the adc de creases at lower throughput rates. figure 35 shows the typical power consumption over a wide range of throughput rates. serial digital interface conversion data is accessed with an spi-compatible serial interface. the interface consists of the serial clock (sclk), serial data output (sdata), and chip select (cs ). the serial interface is designed around using 16 sclk cycles to perform an autozero on the sar comparator and additional sclk cycles for sar comparator decisions (12 slcks in the 12-bit device, 10 sclks in the 10-bit device, and 8 sclks in the 8-bit device). if short cycling is not used, all converter throughput cycles take 16 sclks. the sdata output goes low after the last conversion decision has been presented to the sdata output, as shown in figures 32, 33, and 34. data format output data is encoded in two?s complement format as shown in table 1. the voltage levels in the table are idealized and don?t account for any gain/offset errors or noise. terminology signal-to-(noise + distortion) ratio (sinad) this is the measured ratio of sign al-to-(noise + distortion) at the output of the adc. the signal is the rms amplitude of the fundamental. noise is the sum of all nonfundamental signals up to half the sampling frequency ( f s /2), excluding dc. the ratio is dependent on the number of quantization levels in the digitization process; the more levels, the smaller the quantization noise. the theoretical signal-to-(noise + distortion) ratio for an ideal n-bit converter with a sine wave input is given by equation 1: thus, for a 12-bit converter this is 74db, and for a 10-bit this is 62db. total harmonic distortion total harmonic distortion (thd) is the ratio of the rms sum of harmonics to the fundamental. for the isl26712/10/08, it is defined as equation 2: where v 1 i s the rms amplitude of the fundamental and v 2 , v 3 , v 4 , v 5 , and v 6 are the rms amplitudes of the second to the sixth harmonics. peak harmonic or spurious noise (sfdr) peak harmonic or spurious noise is defined as the ratio of the rms value of the next largest component in the adc output spectrum (up to f s /2 and excluding dc) to the rms value of the 0.01 0.1 1 10 100 0 50 100 150 200 250 300 350 throughput (ksps) power (mw) v dd = 3v v dd = 5v figure 35. power consumption vs throughput rate table 1. output codes - differential input voltage two?s complement (12-bit) >(vfs-1.5 lsb) 7ff vfs-1.5 lsb 7ff ... 7fe -0.5 lsb 000 ? fff -vfs +0.5 lsb 801 ? 800 note: vfs in the table above equals the voltage between ain+ and ain-. differential full scale is equal to 2* vref. signal-to-(noise + distortion) 6.02 n 1.76 + () db = (eq. 1) (eq. 2) thd db () 20 v 2 2 v 3 2 v 4 2 v 5 2 v 6 2 ++++ v 1 2 ----------------------------------------------------------------------- - log =
isl26712, isl26710, ISL26708 18 fn7999.3 september 5, 2012 fundamental. also referred to as spurious free dynamic range (sfdr). normally, the value of this specification is determined by the largest harmonic in the spectrum, but for adcs where the harmonics are buried in the noise floor, it will be a noise peak. intermodulation distortion with inputs consisting of sine waves at two frequencies, fa and fb, any active device with nonlineariti es will create distortion products at sum and difference frequencies of mfa nfb where m and n = 0, 1, 2 or 3. intermodulation di stortion terms are those for which neither m nor n are equal to zero. for example, the second order terms include (fa + fb) and (fa ? fb), while the third order terms include (2fa + fb), (2fa ? fb), (fa + 2fb), and (fa ?2fb). the isl26712/10/08 is tested using the ccif standard, where two input frequencies near the top end of the input bandwidth are used. in this case, the se cond order terms are usually distanced in frequency from the original sine waves, while the third order terms are usually at a frequency close to the input frequencies. as a result, the second and third order terms are specified separately. the calculation of the intermodulation distortion is as per the thd specification, where it is the ratio of the rms sum of the individual distortion products to the rms amplitude of the sum of the fu ndamentals expressed in dbs. aperture delay this is the amount of time from the leading edge of the sampling clock until the adc actually takes the sample. aperture jitter this is the sample-to-sample vari ation in the effective point in time at which the actual sample is taken. full power bandwidth the full power bandwidth of an adc is that input frequency at which the amplitude of the reconstructed fundamental is reduced by 3db for a full-scale input. common-mode rejection ratio (cmrr) the common-mode rejection ratio is defined as the ratio of the power in the adc output at full-sca le frequency, f, to the power of a 250mv p-p sine wave applied to the common-mode voltage of ain+ and ain? of frequency fs shown in equation 3: pfl is the power at frequency f in the adc output; pfs is the power at frequency fs in the adc output. integral nonlinearity (inl) this is the maximum deviation from a straight line passing through the endpoints of the adc transfer function. differential nonlinearity (dnl) this is the difference between the measured and the ideal 1 lsb change between any two adjacent codes in the adc. zero-code error this is the deviation of the midsca le code transition (111...111 to 000...000) from the ideal ain+ ? ain? (i.e., 0 lsb). positive gain error this is the deviation of the last code transition (011...110 to 011...111) from the ideal ain+ ? ain? (i.e., +ref ? 1 lsb), after the zero code error has been adjusted out. negative gain error this is the deviation of the first code transition (100...000 to 100...001) from the ideal ain+ ? ain? (i.e., ? ref + 1 lsb), after the zero code error has been adjusted out. track and hold acquisition time the track and hold acquisition time is the minimum time required for the track and hold amplifier to remain in track mode for its output to reach and settle to within 0.5 lsb of the applied input signal. power supply rejection ratio (psrr) the power supply rejection ratio is defined as the ratio of the power in the adc output at full-scale frequency, f, to adc vdd supply of frequency f s . the frequency of this input varies from 1khz to 1mhz as shown by equation 4. pf is the power at frequency f in the adc output; pfs is the power at frequency f s in the adc output. application hints grounding and layout the printed circuit board that houses the isl26712/10/08 should be designed so that the analog and digital sections are separated and confined to certain areas of the board. this facilitates the use of ground planes that can be easily separated. a minimum etch technique is gene rally best for ground planes since it gives the best shielding. digital and analog ground planes should be joined in only one pl ace, and the connection should be a star ground point established as close to the gnd pin on the isl26712/10/08 as possible. avoid running digital lines under the device, as this will couple noise onto the die. the analog ground plane should be allowed to run under the isl26712/10/08 to avoid noise coupling. the power supply lines to the device should use as large a trace as possible to provide low impedance paths and reduce the effects of glitches on the power supply line. fast switching signals, such as clocks, should be shielded with digital ground to avoid radiating noise to other sections of the board, and clock signals should never run near the analog inputs. avoid crossover of digital and anal og signals. traces on opposite sides of the board should run at right angles to each other. this reduces the effects of feed-through the board. a microstrip technique is by far the best but is not always possible with a double-sided board. in this technique, the component side of the board is dedicated to ground planes, while signals are placed on the solder side. good decoupling is also important. all analog supplies should be decoupled with f tantalum capacitors in parallel with 0.1 f capacitors to gnd. to achieve the best from these decoupling components, they must be placed as close as possible to the device. (eq. 3) cmrr db () 10 pfl pfs ? () log = (eq. 4) psrr db () 10 pf pfs ? () log =
isl26712, isl26710, ISL26708 19 intersil products are manufactured, assembled and tested utilizing iso9000 quality systems as noted in the quality certifications found at www.intersil.com/design/quality intersil products are sold by description only. intersil corporat ion reserves the right to make changes in circuit design, soft ware and/or specifications at any time without notice. accordingly, the reader is cautioned to verify that data sheets are current before placing orders. information furnished by intersil is believed to be accurate and reliable. however, no responsi bility is assumed by intersil or its subsid iaries for its use; nor for any infringem ents of patents or other rights of third parties which may result from its use. no license is granted by implication or otherwise under any patent or patent rights of i ntersil or its subsidiaries. for information regarding intersil corporation and its products, see www.intersil.com fn7999.3 september 5, 2012 for additional products, see www.intersil.com/product_tree products intersil corporation is a leader in the design and manufacture of high-performance analog semico nductors. the company's product s address some of the industry's fastest growing markets, such as , flat panel displays, cell phones, handheld products, and noteb ooks. intersil's product families address power management and analog signal processing functions. go to www.intersil.com/products for a complete list of intersil product families. for a complete listing of applications, rela ted documentation and related parts, please see the respective device information p age on intersil.com: isl26712,isl26710, ISL26708 to report errors or suggestions for this datasheet, please go to: www.intersil.com/askourstaff fits are available from our website at: http://rel.intersil.co m/reports/search.php revision history the revision history provided is for informational purposes only and is believed to be accurate, but not warranted. please go t o web to make sure you have the latest revision. date revision change march 14, 2012 fn7999.0 initial release. may 30, 2012 fn7999.1 page 3, ordering information: removed ?coming soon? from all sot 23 parts. june 20, 2012 fn7999.2 updated figure 25, ?ideal transfer characteristics,? on page 13. updated table 1 on page 17. august 22, 2012 fn7999.3 bolded applicable mi n max specs in ?electrical specificatio ns? and ?timing specifications? tables.
isl26712, isl26710, ISL26708 20 fn7999.3 september 5, 2012 small outline transistor pl astic packages (sot23-8) d e 1 e c l e b c l a2 a a1 c l 0.20 (0.008) m 0.10 (0.004) c c -c- seating plane 1234 5 6 87 e1 c l c view c view c l r1 r 4x 1 4x 1 gauge plane l1 seating l2 c plane c base metal with c1 b1 plating b p8.064 8 lead small outline transistor plastic package symbol inches millimeters notes min max min max a 0.036 0.057 0.90 1.45 - a1 0.000 0.0059 0.00 0.15 - a2 0.036 0.051 0.90 1.30 - b 0.009 0.015 0.22 0.38 - b1 0.009 0.013 0.22 0.33 c 0.003 0.009 0.08 0.22 6 c1 0.003 0.008 0.08 0.20 6 d 0.111 0.118 2.80 3.00 3 e 0.103 0.118 2.60 3.00 - e1 0.060 0.067 1.50 1.70 3 e 0.0256 ref 0.65 ref - e1 0.0768 ref 1.95 ref - l 0.014 0.022 0.35 0.55 4 l1 0.024 ref. 0.60 ref. l2 0.010 ref. 0.25 ref. n8 85 r 0.004 - 0.10 - r1 0.004 0.010 0.10 0.25 0 o 8 o 0 o 8 o - rev. 2 9/03 notes: 1. dimensioning and tolerance per asme y14.5m-1994. 2. package conforms to eiaj sc-74 and jedec mo178ba. 3. dimensions d and e1 are exclusive of mold flash, protrusions, or gate burrs. 4. footlength l measured at reference to gauge plane. 5. ?n? is the number of terminal positions. 6. these dimensions apply to the flat section of the lead between 0.08mm and 0.15mm from the lead tip. 7. controlling dimension: millimeter. converted inch dimensions are for reference only
isl26712, isl26710, ISL26708 21 fn7999.3 september 5, 2012 package outline drawing l8.3x3i 8 lead thin dual flat no-lead plastic package rev 1 6/09 located within the zone indicated. the pin #1 identifier may be unless otherwise specified, tolerance : decimal 0.05 tiebar shown (if present) is a non-functional feature. the configuration of the pin #1 identifier is optional, but must be between 0.15mm and 0.30mm from the terminal tip. dimension applies to the metallized terminal and is measured dimensions in ( ) for reference only. dimensioning and tolerancing conform to amse y14.5m-1994. 6. either a mold or mark feature. 3. 5. 4. 2. dimensions are in millimeters. 1. notes: bottom view detail "x" typical recommended land pattern top view side view c 0 . 2 ref 0 . 05 max. 0 . 00 min. 5 3.00 a b 3.00 (4x) 0.15 6 pin 1 index area pin #1 index area 6x 0.65 1.64 +0.10/ - 0.15 8 1 8x 0.400 0.10 6 max 0.80 see detail "x" 0.08 0.10 c c c ( 2.80 ) (1.64) ( 8 x 0.30) ( 8x 0.60) ( 2.38 ) ( 1.95) 2.38 0.10 8x 0.30 a mc b 4 2x 1.950 +0.10/ - 0.15 (6x 0.65) 4 5 pin 1

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